From ddb4f151c8e49b9e3108d2dfe7685d8fe83c42c5 Mon Sep 17 00:00:00 2001 From: natrixaeria Date: Sun, 17 Nov 2019 14:33:03 +0100 Subject: Disable PIC through IO port write --- kernel/src/interrupts/apic.rs | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'kernel/src/interrupts/apic.rs') diff --git a/kernel/src/interrupts/apic.rs b/kernel/src/interrupts/apic.rs index 14f6169..3d42ba9 100644 --- a/kernel/src/interrupts/apic.rs +++ b/kernel/src/interrupts/apic.rs @@ -97,11 +97,8 @@ pub struct Apic { impl Apic { pub fn new() -> Option { - use core::fmt::Write; - let mut stdout = crate::io::vga_text::OStream::new(); - stdout.clear(); - if !is_apic() { return None; } + Self::disable_pic(); let mut base_apic = unsafe { Msr::new(APIC_BASE_MSR).read() }; let mut apic = Self::from_base_apic(base_apic); @@ -113,12 +110,19 @@ impl Apic { apic.set(ApicRegister::TaskPriority, 0); apic.set(ApicRegister::LvtPerformanceMonitor, APIC_NMI); - apic.set(ApicRegister::LvtLint0, 0); - apic.set(ApicRegister::LvtLint1, 0); + apic.set(ApicRegister::LvtLint0, APIC_DISABLE); + apic.set(ApicRegister::LvtLint1, APIC_DISABLE); Some(apic) } + pub fn disable_pic() { + unsafe { + x86_64::instructions::port::PortWriteOnly::new(0xa1).write(0xffu8); + x86_64::instructions::port::PortWriteOnly::new(0x21).write(0xffu8); + } + } + fn from_base_apic(base_apic: u64) -> Self { Self { regs: ((base_apic >> 12) & 0xfffffffff) as *mut [u32; 1024] -- cgit v1.2.3-70-g09d2