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authornatrixaeria <upezu@student.kit.edu>2019-11-15 20:01:26 +0100
committernatrixaeria <upezu@student.kit.edu>2019-11-15 20:01:26 +0100
commit57850278fd6540dbf485db38d6819cbf40e0adf0 (patch)
treea1a57019e739333557eea469ac57c75b85990673 /kernel/src/interrupts
parent307571308b115eb737281711c780fa4cd1ed837f (diff)
Add apic module
Diffstat (limited to 'kernel/src/interrupts')
-rw-r--r--kernel/src/interrupts/apic.rs121
-rw-r--r--kernel/src/interrupts/mod.rs1
2 files changed, 122 insertions, 0 deletions
diff --git a/kernel/src/interrupts/apic.rs b/kernel/src/interrupts/apic.rs
new file mode 100644
index 0000000..519caf2
--- /dev/null
+++ b/kernel/src/interrupts/apic.rs
@@ -0,0 +1,121 @@
+use x86_64::registers::model_specific::Msr;
+
+#[cfg(target_arch = "x86_64")]
+const APIC_FLAG: u64 = 0x0800;
+const APIC_BASE_MSR: u32 = 0x1b;
+
+pub fn is_x2apic() -> bool {
+ let info: u32;
+ unsafe {
+ asm!("cpuid" : "={ecx}" (info) : "{eax}" (1) : "memory");
+ }
+ info & (1 << 21) != 0
+}
+
+pub fn is_apic() -> bool {
+ let info: u32;
+ unsafe {
+ asm!("cpuid" : "={edx}" (info) : "{eax}" (1) : "memory");
+ }
+ info & (1 << 9) != 0
+}
+
+pub fn set_apic_base(v: u64) {
+ unsafe { Msr::new(APIC_BASE_MSR).write(v) }
+}
+
+#[repr(C)]
+pub struct InterruptCommand {
+ low: u32,
+ _rsv: [u32; 3],
+ high: u32
+}
+
+#[repr(isize)]
+pub enum ApicRegister {
+ ApicId=8,
+ ApicVer=12,
+ TaskPriority=32,
+ ArbitrationPriority=36,
+ ProcessorPriority=40,
+ EndOfInterrupt=44,
+ LogicalDst=52,
+ DstFmt=56,
+ SpuriousInterruptVec=60,
+ InService=64,
+ TriggerMode=96,
+ InterruptRequest=128,
+ ErrorStatus=160,
+ InterruptCommand=192,
+ InterruptCommandHigh=196,
+ LvtTimer=200,
+ LvtThermalSensor=204,
+ LvtPerformanceMonitor=208,
+ LvtLint1=212,
+ LvtError=220,
+ TimerInitialCount=224,
+ TimerCurrentCount=228,
+ TimerDivideConfig=248,
+ ExtApicFeature=256,
+ ExtApicControl=260,
+ SpecificEndOfInterrupt=264,
+ InterruptEnable=288,
+ ExtInterruptLocalVectorTable=320,
+}
+
+#[repr(C)]
+pub struct ApicRegisters {
+ regs32: *mut [u32; 1024],
+}
+
+impl ApicRegisters {
+ fn from_base_apic(base_apic: u64) -> Self {
+ Self { regs32:
+ ((base_apic >> 12) & 0xfffffffff) as *mut [u32; 1024]
+ }
+ }
+
+ fn ptr(&self) -> *const u32 { self.regs32 as *const u32 }
+ fn ptr_mut(&mut self) -> *mut u32 { self.regs32 as *mut u32 }
+
+ pub fn get(&self, register: ApicRegister) -> u32 {
+ unsafe { self.ptr().offset(register as isize).read_volatile() }
+ }
+
+ pub fn set(&mut self, register: ApicRegister, val: u32) {
+ unsafe { self.ptr_mut().offset(register as isize).write_volatile(val) }
+ }
+
+ pub fn set_interrupt_command(&mut self, dst: u8, v: u8) {
+ let (dst, v): (u32, u32) = (dst.into(), v.into());
+ self.set(ApicRegister::InterruptCommandHigh, dst << 24);
+ self.set(ApicRegister::InterruptCommand, v)
+ }
+}
+
+pub struct Apic {
+ base_apic: u64,
+ regs: ApicRegisters,
+}
+
+impl Apic {
+ pub fn new() -> Option<Self> {
+ use core::fmt::Write;
+ let mut stdout = crate::io::vga_text::OStream::new();
+ stdout.clear();
+
+ if !is_apic() { return None; }
+ let mut base_apic = unsafe { Msr::new(APIC_BASE_MSR).read() };
+ let mut regs = ApicRegisters::from_base_apic(base_apic);
+
+ let spurious = regs.get(ApicRegister::SpuriousInterruptVec) | 0x1ff;
+
+ unsafe { Msr::new(APIC_BASE_MSR).write(base_apic | APIC_FLAG) };
+
+ regs.set(ApicRegister::SpuriousInterruptVec, spurious);
+
+ Some(Self {
+ base_apic, regs
+ })
+ }
+}
diff --git a/kernel/src/interrupts/mod.rs b/kernel/src/interrupts/mod.rs
index 4ff3c4d..9753b6b 100644
--- a/kernel/src/interrupts/mod.rs
+++ b/kernel/src/interrupts/mod.rs
@@ -1,3 +1,4 @@
+pub mod apic;
pub mod exceptions;
pub mod gdt;
pub mod idt;