diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-02 09:13:25 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 13:56:09 +0200 |
| commit | 13ea8b3584c09f0ab94d5447ff2965d255329a88 (patch) | |
| tree | b946941a368f8efc0265cb5c49c602c600ee143c | |
| parent | 20e63d3948985672b9e8efa98ff3643d91378e84 (diff) | |
arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
Add Gigabit Ethernet{0,1} nodes to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c013d4fbe9f7..c8aadbe55278 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -365,6 +365,46 @@ status = "disabled"; }; + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + phyrst: usbphy-ctrl@11c40000 { reg = <0 0x11c40000 0 0x10000>; /* place holder */ |