diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2021-03-02 15:24:58 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-03-26 13:10:25 +0100 |
| commit | 19221e3083020bd9537624caa0ee0145ed92ba36 (patch) | |
| tree | 685db67661ad55cdabfbe0f19c2e23f852001920 | |
| parent | ef85bb582c41524e9e68dfdbde48e519dac4ab3d (diff) | |
soc/tegra: pmc: Fix imbalanced clock disabling in error code path
The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/soc/tegra/pmc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2e7692dbdd61..7a77e8d06163 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -660,7 +660,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, err = tegra_powergate_enable_clocks(pg); if (err) - goto disable_clks; + goto powergate_off; usleep_range(10, 20); |