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| author | Yifan Zhang <yifan1.zhang@amd.com> | 2024-05-23 14:10:30 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-06-05 11:02:37 -0400 |
| commit | 301dfbfc84e81f2ee80a84574432df52125d2b4a (patch) | |
| tree | c49c5fed1101186a3d6535458fcaf96e59b609c3 | |
| parent | b7e2170b87938f8a4664018111de3ba8c1ed2db3 (diff) | |
drm/amdgpu: disable lane0 L1TLB and enable lane1 L1TLB
This patch to disable lane0 L1TLB and enable lane1 L1TLB.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c index b22751a25c9c..8928f9160822 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c @@ -33,6 +33,10 @@ #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 +#define regDAGB0_L1TLB_REG_RW_3_3 0x00a4 +#define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX 1 +#define regDAGB1_L1TLB_REG_RW_3_3 0x0163 +#define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX 1 static const char *mmhub_client_ids_v3_3[][2] = { [0][0] = "VMC", @@ -396,6 +400,12 @@ static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp); } +static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev) +{ + WREG32_SOC15(MMHUB, 0, regDAGB0_L1TLB_REG_RW_3_3, 0); + WREG32_SOC15(MMHUB, 0, regDAGB1_L1TLB_REG_RW_3_3, 3); +} + static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) { /* GART Enable. */ @@ -412,6 +422,9 @@ static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) /* standalone alone walker init */ mmhub_v3_3_init_saw_regs(adev); + /* enable mmhub tls */ + mmhub_v3_3_enable_tls(adev); + return 0; } |