diff options
| author | Dorcas AnonoLitunya <anonolitunya@gmail.com> | 2023-10-16 23:14:10 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-10-17 15:38:00 +0200 |
| commit | 7826b6338b144c99fcaa5c283eead3c6b320be1d (patch) | |
| tree | 099108271295610531f9d0918d088651181ecd3d | |
| parent | 474adce40776b2de1641c4e6d9237559dfa3f842 (diff) | |
Staging: sm750fb: Rename dispControl
Rename variable dispControl to disp_control. This follows
snakecase naming convention and ensures a consistent naming style
throughout the file. Issue found by checkpatch.
Mutes the following checkpatch error:
CHECK: Avoid CamelCase: <dispControl>
Signed-off-by: Dorcas AnonoLitunya <anonolitunya@gmail.com>
Link: https://lore.kernel.org/r/20231016201434.7880-4-anonolitunya@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_mode.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index 431b273a347a..fc3db09de9ae 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -15,7 +15,7 @@ */ static unsigned long display_control_adjust_SM750LE(struct mode_parameter *mode_param, - unsigned long dispControl) + unsigned long disp_control) { unsigned long x, y; @@ -36,42 +36,42 @@ display_control_adjust_SM750LE(struct mode_parameter *mode_param, ((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK)); /* - * Assume common fields in dispControl have been properly set before + * Assume common fields in disp_control have been properly set before * calling this function. - * This function only sets the extra fields in dispControl. + * This function only sets the extra fields in disp_control. */ /* Clear bit 29:27 of display control register */ - dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK; + disp_control &= ~CRT_DISPLAY_CTRL_CLK_MASK; /* Set bit 29:27 of display control register for the right clock */ /* Note that SM750LE only need to supported 7 resolutions. */ if (x == 800 && y == 600) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL41; else if (x == 1024 && y == 768) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL65; else if (x == 1152 && y == 864) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL80; else if (x == 1280 && y == 768) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL80; else if (x == 1280 && y == 720) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL74; else if (x == 1280 && y == 960) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL108; else if (x == 1280 && y == 1024) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL108; else /* default to VGA clock */ - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL25; /* Set bit 25:24 of display controller */ - dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT); + disp_control |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT); /* Set bit 14 of display controller */ - dispControl |= DISPLAY_CTRL_CLOCK_PHASE; + disp_control |= DISPLAY_CTRL_CLOCK_PHASE; - poke32(CRT_DISPLAY_CTRL, dispControl); + poke32(CRT_DISPLAY_CTRL, disp_control); - return dispControl; + return disp_control; } /* only timing related registers will be programed */ |