diff options
| author | Imre Deak <imre.deak@intel.com> | 2024-04-17 01:10:01 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2024-04-19 17:05:36 +0300 |
| commit | 854ff3d9b8bb5187cd753c2ac59248c83f42fc99 (patch) | |
| tree | d52a7eb91a6baff668b8b87c503384b055e42339 | |
| parent | f1d6aec41f13aad3c3ff8daa9fddb38539afe8f6 (diff) | |
drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit
The expected link symbol clock unit when calculating the DSC DPT bpp
limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit
based on the crtc clock. As opposed to this port_clock is used - which
has a 10 kbits/sec unit - with the resulting symbol clock in 10
kSymbols/sec units (disregarding the rounding error for the 13.5Gbps
rate). Fix the calculation using the expected 10x factor.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-3-imre.deak@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d43617734009..196eeead8cf0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp { if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { int output_bpp = bpp; - /* DisplayPort 2 128b/132b, bits per lane is always 32 */ - int symbol_clock = crtc_state->port_clock / 32; + int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); if (output_bpp * adjusted_mode->crtc_clock >= symbol_clock * 72) { |