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authorPaul Elder <paul.elder@ideasonboard.com>2022-04-06 17:33:54 +0200
committerShawn Guo <shawnguo@kernel.org>2022-05-05 09:24:41 +0800
commit8b3dd27bfe47abe30450d01077983497aa1a159f (patch)
tree6f612404c17cd37ee1be2d46f02568dff3fa80a9
parent3123109284176b1532874591f7c81f3837bbdc17 (diff)
dt-bindings: soc: Add i.MX8MP media block control DT bindings
The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral providing access to the NoC and ensuring proper power sequencing of the peripherals within the MEDIAMIX domain. Add DT bindings for it. There is already a driver for block controls of other SoCs in the i.MX8M family, so these bindings will expand upon that. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml104
-rw-r--r--include/dt-bindings/power/imx8mp-power.h10
2 files changed, 114 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..21d3ee486295
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP Media Block Control
+
+maintainers:
+ - Paul Elder <paul.elder@ideasonboard.com>
+
+description:
+ The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
+ providing access to the NoC and ensuring proper power sequencing of the
+ peripherals within the MEDIAMIX domain.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mp-media-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ maxItems: 10
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: mipi-dsi1
+ - const: mipi-csi1
+ - const: lcdif1
+ - const: isi
+ - const: mipi-csi2
+ - const: lcdif2
+ - const: isp
+ - const: dwe
+ - const: mipi-dsi2
+
+ clocks:
+ items:
+ - description: The APB clock
+ - description: The AXI clock
+ - description: The pixel clock for the first CSI2 receiver (aclk)
+ - description: The pixel clock for the second CSI2 receiver (aclk)
+ - description: The pixel clock for the first LCDIF (pix_clk)
+ - description: The pixel clock for the second LCDIF (pix_clk)
+ - description: The core clock for the ISP (clk)
+ - description: The MIPI-PHY reference clock used by DSI
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: cam1
+ - const: cam2
+ - const: disp1
+ - const: disp2
+ - const: isp
+ - const: phy
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/power/imx8mp-power.h>
+
+ media_blk_ctl: blk-ctl@32ec0000 {
+ compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
+ reg = <0x32ec0000 0x138>;
+ power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
+ <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
+ <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
+ <&mipi_phy2_pd>;
+ power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
+ "mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+ clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
+ "isp", "phy";
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 9f90c40a2c6c..bc8458f1e725 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -32,4 +32,14 @@
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
+#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
+#define IMX8MP_MEDIABLK_PD_ISI 3
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
+#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
+#define IMX8MP_MEDIABLK_PD_ISP 6
+#define IMX8MP_MEDIABLK_PD_DWE 7
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
+
#endif