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| author | Ludovic Barre <ludovic.barre@st.com> | 2019-03-01 09:47:00 +0100 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@st.com> | 2019-04-11 11:22:00 +0200 |
| commit | 8d17cf7a8e8b1ed3e979b1740401e72150fca5e9 (patch) | |
| tree | 7dd1c4acb9a96586a030677f80f269b1f8d0c517 | |
| parent | 30a8e03a1f71ec0bd0208944fac10f7e0433fe3a (diff) | |
ARM: dts: stm32: add sdmmc1 support on stm32mp157c
This patch adds support of sdmmc1 on stm32mp157c.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
| -rw-r--r-- | arch/arm/boot/dts/stm32mp157c.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index f8bbfff5950b..667f5606268b 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1050,6 +1050,20 @@ status = "disabled"; }; + sdmmc1: sdmmc@58005000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58005000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + crc1: crc@58009000 { compatible = "st,stm32f7-crc"; reg = <0x58009000 0x400>; |