diff options
| author | Xianwei Zhao <xianwei.zhao@amlogic.com> | 2024-06-03 18:04:33 +0800 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2024-06-03 12:29:37 +0200 |
| commit | c1380adf2e8680a00dedaf1b25c19beadbbe5bbd (patch) | |
| tree | b3b703ee6b9d906bee4c34924852e88ac4b3f586 | |
| parent | 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0 (diff) | |
clk: meson: s4: fix fixed_pll_dco clock
The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.
Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| -rw-r--r-- | drivers/clk/meson/s4-pll.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index d2650d96400c..707c107a5291 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = { .shift = 0, .width = 8, }, + .frac = { + .reg_off = ANACTRL_FIXPLL_CTRL1, + .shift = 0, + .width = 17, + }, .n = { .reg_off = ANACTRL_FIXPLL_CTRL0, .shift = 10, |