diff options
| author | Jérémie Dautheribes <jeremie.dautheribes@bootlin.com> | 2024-02-22 11:31:16 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2024-02-26 11:38:44 +0000 |
| commit | d2ed0774b6334ce3986c5efb17ab9c4095b8d969 (patch) | |
| tree | 1afe756a8abfb45bbb3b20c9eac3d2f5faca799f | |
| parent | 95f4fa1f459a69827d752bd55205af7c55b76e4e (diff) | |
net: phy: dp83826: Add support for phy-mode configuration
The TI DP83826 PHY can operate in either MII mode or RMII mode.
By default, it is configured by straps.
It can also be configured by writing to the bit 5 of register 0x17 - RMII
and Status Register (RCSR).
When phydev->interface is rmii, rmii mode must be enabled, otherwise
mii mode must be set.
This prevents misconfiguration of hw straps.
Signed-off-by: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/dp83822.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index 30f2616ab1c2..2d8275e59dcc 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -100,6 +100,7 @@ #define DP83822_WOL_CLR_INDICATION BIT(11) /* RCSR bits */ +#define DP83822_RMII_MODE_EN BIT(5) #define DP83822_RGMII_MODE_EN BIT(9) #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) @@ -500,6 +501,16 @@ static int dp83826_config_init(struct phy_device *phydev) u16 val, mask; int ret; + if (phydev->interface == PHY_INTERFACE_MODE_RMII) + ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RMII_MODE_EN); + else + ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RMII_MODE_EN); + + if (ret) + return ret; + if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, |