diff options
| author | Lang Yu <Lang.Yu@amd.com> | 2023-10-02 00:10:42 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-13 11:01:37 -0400 |
| commit | faeddb6eab220c2cafa58e6de9e4a6fcd9a36d19 (patch) | |
| tree | c7336e32dd9cf163c979ffb4fdfd387a16a4b204 | |
| parent | 10406abe036b97a9c3549779a41c93ca488a0b7b (diff) | |
drm/amdgpu/umsch: enable doorbell for umsch
Program vcn_doorbell_range with vcn_ring0_1.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 8889006cdd9d..1c523eb5f342 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -553,7 +553,7 @@ int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch) struct amdgpu_ring *ring = &umsch->ring; ring->vm_hub = AMDGPU_MMHUB0(0); - ring->use_doorbell = 0; + ring->use_doorbell = true; ring->no_scheduler = true; ring->doorbell_index = (AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 1) + 6; diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c index 16b291ca3beb..63917e2b51b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c @@ -217,7 +217,8 @@ static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch) data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1); WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data); - adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, ring->doorbell_index, 0); + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); |