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author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-11-27 11:19:09 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-11-27 11:19:09 -0800 |
commit | 91dbbe6c9ffe5eded9a3e75d773ff92da8d2bc57 (patch) | |
tree | 30c98b08c3906a35d34327eff7725618c9045588 /Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | |
parent | c94696977527f69cbb41aa6a9af9d1991895d002 (diff) | |
parent | 8d4f1e05ff821a5d59116ab8c3a30fcae81d8597 (diff) |
Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-v updates from Palmer Dabbelt:
- Support for pointer masking in userspace
- Support for probing vector misaligned access performance
- Support for qspinlock on systems with Zacas and Zabha
* tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits)
RISC-V: Remove unnecessary include from compat.h
riscv: Fix default misaligned access trap
riscv: Add qspinlock support
dt-bindings: riscv: Add Ziccrse ISA extension description
riscv: Add ISA extension parsing for Ziccrse
asm-generic: ticket-lock: Add separate ticket-lock.h
asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock
riscv: Implement xchg8/16() using Zabha
riscv: Implement arch_cmpxchg128() using Zacas
riscv: Improve zacas fully-ordered cmpxchg()
riscv: Implement cmpxchg8/16() using Zabha
dt-bindings: riscv: Add Zabha ISA extension description
riscv: Implement cmpxchg32/64() using Zacas
riscv: Do not fail to build on byte/halfword operations with Zawrs
riscv: Move cpufeature.h macros into their own header
KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test
RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests
riscv: hwprobe: Export the Supm ISA extension
riscv: selftests: Add a pointer masking test
riscv: Allow ptrace control of the tagged address ABI
...
Diffstat (limited to 'Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml')
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