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| author | Srujana Challa <schalla@marvell.com> | 2021-01-15 19:22:22 +0530 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-01-22 14:58:03 +1100 |
| commit | 43ac0b824f1cb7c63c5fe98ea2b80ec480412601 (patch) | |
| tree | 2081b7bc1caf3a0fa2e963a394993b6afcff966b /README | |
| parent | fe16eceab0463c160a333b7df4edd707f3a24d5c (diff) | |
crypto: octeontx2 - load microcode and create engine groups
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec
symmetric engines(IEs), and asymmetric engines (AEs).
Each engine receives CPT instructions from the engine groups it has
subscribed to. This patch loads microcode, configures three engine
groups(one for SEs, one for IEs and one for AEs), and configures
all engines.
Signed-off-by: Suheil Chandran <schandran@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'README')
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