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authorIngo Molnar <mingo@kernel.org>2016-06-14 11:04:13 +0200
committerIngo Molnar <mingo@kernel.org>2016-06-14 11:04:13 +0200
commit07f9f22087a94e8162f77ee997c52a23f158aee8 (patch)
tree04bfe0395c6aa95bae5c6983c3433d9ac8eb7731 /arch/arc/include/asm/pgtable.h
parent03c041c5bf6ed584dff36b7cd509e0146a124277 (diff)
parentb7fa30c9cc48c4f55663420472505d3b4f6e1705 (diff)
Merge branch 'sched/urgent' into sched/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arc/include/asm/pgtable.h')
-rw-r--r--arch/arc/include/asm/pgtable.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 034bbdc0ff61..858f98ef7f1b 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -47,7 +47,7 @@
* Page Tables are purely for Linux VM's consumption and the bits below are
* suited to that (uniqueness). Hence some are not implemented in the TLB and
* some have different value in TLB.
- * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in
+ * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in
* seperate PD0 and PD1, which combined forms a translation entry)
* while for PTE perspective, they are 8 and 9 respectively
* with MMU v3: Most bits (except SHARED) represent the exact hardware pos