diff options
| author | Mark Brown <broonie@linaro.org> | 2013-10-03 17:29:05 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-10-03 17:29:05 +0100 |
| commit | 8e9c4aa4e7bd600d30e15ec82be9b670a1ec3da9 (patch) | |
| tree | 3b19eb54c684e36feab568078018dea31c43a79f /arch/arm/mach-imx/system.c | |
| parent | d60336e2f136287de821901d4a1b56179a0f7b69 (diff) | |
| parent | 1d73ad298d1bfeee5d77c19e5cd667c551e30632 (diff) | |
Merge remote-tracking branch 'asoc/fix/fsl' into asoc-fsl
Conflicts:
sound/soc/fsl/fsl_ssi.c
Diffstat (limited to 'arch/arm/mach-imx/system.c')
| -rw-r--r-- | arch/arm/mach-imx/system.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 64ff37ea72b1..80c177c36c5f 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -117,6 +117,17 @@ void __init imx_init_l2cache(void) /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); val |= 0x70800000; + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (cpu_is_imx6q()) + val &= ~(1 << 30 | 1 << 23); writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); |