diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-05-16 16:35:25 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-16 16:35:25 +0200 |
| commit | 3c0dec5f58b3c7b3627715126d1bf9b030a076f0 (patch) | |
| tree | 4bf8f56fca3bf6be109209b116fc8e32cb2e0f9e /arch/arm/mach-kirkwood/pcie.c | |
| parent | fcd8d84a585f3578a9ebdd27e757495a27415322 (diff) | |
| parent | 7e0fa1b5fa91d9aa456d102c273b2cf0f2e95d39 (diff) | |
Merge branch 'clk-next' of git://git.linaro.org/people/mturquette/linux into next/clock
* 'clk-next' of git://git.linaro.org/people/mturquette/linux:
clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().
clk: Provide dummy clk_unregister()
ARM: Kirkwood: Replace clock gating
ARM: Orion: Audio: Add clk/clkdev support
ARM: Orion: PCIE: Add support for clk
ARM: Orion: XOR: Add support for clk
ARM: Orion: CESA: Add support for clk
ARM: Orion: SDIO: Add support for clk.
ARM: Orion: NAND: Add support for clk, if there is one.
ARM: Orion: EHCI: Add support for enabling clocks
ARM: Orion: SATA: Add per channel clk/clkdev support.
ARM: Orion: UART: Get the clock rate via clk_get_rate().
ARM: Orion: WDT: Add clk/clkdev support
ARM: Orion: Eth: Add clk/clkdev support.
ARM: Orion: SPI: Add clk/clkdev support.
ARM: Orion: Add clocks using the generic clk infrastructure.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-kirkwood/pcie.c')
| -rw-r--r-- | arch/arm/mach-kirkwood/pcie.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index f56a0118c1bb..f26d6cff8bab 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -11,6 +11,7 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/slab.h> +#include <linux/clk.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> @@ -19,6 +20,23 @@ #include <plat/addr-map.h> #include "common.h" +static void kirkwood_enable_pcie_clk(const char *port) +{ + struct clk *clk; + + clk = clk_get_sys("pcie", port); + if (IS_ERR(clk)) { + printk(KERN_ERR "PCIE clock %s missing\n", port); + return; + } + clk_prepare_enable(clk); + clk_put(clk); +} + +/* This function is called very early in the boot when probing the + hardware to determine what we actually are, and what rate tclk is + ticking at. Hence calling kirkwood_enable_pcie_clk() is not + possible since the clk tree has not been created yet. */ void kirkwood_enable_pcie(void) { u32 curr = readl(CLOCK_GATING_CTRL); @@ -26,7 +44,7 @@ void kirkwood_enable_pcie(void) writel(curr | CGC_PEX0, CLOCK_GATING_CTRL); } -void __init kirkwood_pcie_id(u32 *dev, u32 *rev) +void kirkwood_pcie_id(u32 *dev, u32 *rev) { kirkwood_enable_pcie(); *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); @@ -163,7 +181,6 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp) static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) { - extern unsigned int kirkwood_clk_ctrl; struct pcie_port *pp; int index; @@ -182,11 +199,11 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) switch (index) { case 0: - kirkwood_clk_ctrl |= CGC_PEX0; + kirkwood_enable_pcie_clk("0"); pcie0_ioresources_init(pp); break; case 1: - kirkwood_clk_ctrl |= CGC_PEX1; + kirkwood_enable_pcie_clk("1"); pcie1_ioresources_init(pp); break; default: |