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authorTudor Ambarus <tudor.ambarus@linaro.org>2023-03-28 10:15:17 +0000
committerNicolas Ferre <nicolas.ferre@microchip.com>2023-03-30 21:20:59 +0200
commit2c0a1faa4da5324a2ad6621b69fb7db26134b994 (patch)
treed28b9262a0ad77caca36796d4f65e1673c1067d9 /arch/arm/mach-moxart
parent46a8a137d8f60929923a609cdddde06e7007b0df (diff)
ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency
sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~33%. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230328101517.1595738-5-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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