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authorArd Biesheuvel <ardb@kernel.org>2022-01-27 12:35:43 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2022-02-05 15:10:51 +1100
commitc8bf850e991a1838964ed8d8426f96cf8d3fbab5 (patch)
tree4845e70ee700096733b810eaab6281dc15441e3b /arch/arm/mach-tegra/Kconfig
parent8daa399edeed4cfa792ccea12beda50d445ab6a0 (diff)
crypto: arm/aes-neonbs-ctr - deal with non-multiples of AES block size
Instead of falling back to C code to deal with the final bit of input that is not a round multiple of the block size, handle this in the asm code, permitting us to use overlapping loads and stores for performance, and implement the 16-byte wide XOR using a single NEON instruction. Since NEON loads and stores have a natural width of 16 bytes, we need to handle inputs of less than 16 bytes in a special way, but this rarely occurs in practice so it does not impact performance. All other input sizes can be consumed directly by the NEON asm code, although it should be noted that the core AES transform can still only process 128 bytes (8 AES blocks) at a time. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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