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author | Trond Myklebust <Trond.Myklebust@netapp.com> | 2012-05-21 10:12:39 -0400 |
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committer | Trond Myklebust <Trond.Myklebust@netapp.com> | 2012-05-21 10:12:39 -0400 |
commit | b3f87b98aa3dc22cc58f970140113b270015cddb (patch) | |
tree | c4aec5996567ad96310f61e9244e799f41bf2625 /arch/arm/plat-omap/dma.c | |
parent | 041245c88a29273788e8eff1353bc6e1f56c61df (diff) | |
parent | 1afeaf5c29aa07db25760d2fbed5c08a3aec3498 (diff) |
Merge branch 'bugfixes' into nfs-for-next
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
-rw-r--r-- | arch/arm/plat-omap/dma.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index ecdb3da0dea9..c58d896cd5c3 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -916,6 +916,13 @@ void omap_start_dma(int lch) l |= OMAP_DMA_CCR_BUFFERING_DISABLE; l |= OMAP_DMA_CCR_EN; + /* + * As dma_write() uses IO accessors which are weakly ordered, there + * is no guarantee that data in coherent DMA memory will be visible + * to the DMA device. Add a memory barrier here to ensure that any + * such data is visible prior to enabling DMA. + */ + mb(); p->dma_write(l, CCR, lch); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; @@ -965,6 +972,13 @@ void omap_stop_dma(int lch) p->dma_write(l, CCR, lch); } + /* + * Ensure that data transferred by DMA is visible to any access + * after DMA has been disabled. This is important for coherent + * DMA regions. + */ + mb(); + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; char dma_chan_link_map[dma_lch_count]; |