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| author | Biju Das <biju.das@bp.renesas.com> | 2019-09-05 07:52:40 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-10-01 09:49:40 +0200 |
| commit | 54ce17dd40fd846a7ac1e87e1103032933d2bd21 (patch) | |
| tree | a377e3a27addb28a179097c950c2ff047fc7841a /arch/arm64/boot/dts/renesas/r8a77970.dtsi | |
| parent | be67c41781cb4c06a4acb0b92db0cbb728e955e2 (diff) | |
dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions
Add all RZ/G2N Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2d ("List of Clocks [RZ/G2N]") of the RZ/G2N Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1567666360-28035-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a77970.dtsi')
0 files changed, 0 insertions, 0 deletions