diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-09-30 11:39:59 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2015-10-09 22:16:51 +0100 |
| commit | d271976dbb31c3ac5653745d03d68c4235d34119 (patch) | |
| tree | 4696526bf1052982df10938f3bbb4bf5bd302d53 /arch/arm64/kernel/head.S | |
| parent | 0e841b04c829f59a5d5745f98d2857f48882efe9 (diff) | |
arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3 sysregs
Contrary to what was originally expected, EL3 firmware can (for whatever
reason) disable GICv3 system register access. In this case, the kernel
explodes very early.
Work around this by testing if the SRE bit sticks or not. If it doesn't,
abort the GICv3 setup, and pray that the firmware has passed a DT that
doesn't contain a GICv3 node.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/kernel/head.S')
| -rw-r--r-- | arch/arm64/kernel/head.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 90d09eddd5b2..351a4de1b1e2 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -498,6 +498,8 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 msr_s ICC_SRE_EL2, x0 isb // Make sure SRE is now set + mrs_s x0, ICC_SRE_EL2 // Read SRE back, + tbz x0, #0, 3f // and check that it sticks msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 3: |