diff options
| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-05-31 18:04:10 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-06-03 20:09:27 +0800 |
| commit | 439057ec3b748b1ff61855d09859f369493e22d8 (patch) | |
| tree | 488f331128a8ba653855b4434dcf1825b12804bb /arch/loongarch/pci | |
| parent | 08145b087e4481458f6075f3af58021a3cf8a940 (diff) | |
LoongArch: Add writecombine support for drm
LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/pci')
0 files changed, 0 insertions, 0 deletions