diff options
| author | Ingo Molnar <mingo@elte.hu> | 2009-04-29 14:46:59 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-04-29 14:47:05 +0200 |
| commit | e7fd5d4b3d240f42c30a9e3d20a4689c4d3a795a (patch) | |
| tree | 4ba588631dd8189a818a91c9e3976526071178b6 /arch/m32r/include/asm/cachectl.h | |
| parent | 1130b0296184bc21806225fd06d533515a99d2db (diff) | |
| parent | 56a50adda49b2020156616c4eb15353e0f9ad7de (diff) | |
Merge branch 'linus' into perfcounters/core
Merge reason: This brach was on -rc1, refresh it to almost-rc4 to pick up
the latest upstream fixes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/m32r/include/asm/cachectl.h')
| -rw-r--r-- | arch/m32r/include/asm/cachectl.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h new file mode 100644 index 000000000000..2aab8f6fff41 --- /dev/null +++ b/arch/m32r/include/asm/cachectl.h @@ -0,0 +1,26 @@ +/* + * cachectl.h -- defines for M32R cache control system calls + * + * Copyright (C) 2003 by Kazuhiro Inaoka + */ +#ifndef __ASM_M32R_CACHECTL +#define __ASM_M32R_CACHECTL + +/* + * Options for cacheflush system call + * + * cacheflush() is currently fluch_cache_all(). + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +/* + * Caching modes for the cachectl(2) call + * + * cachectl(2) is currently not supported and returns ENOSYS. + */ +#define CACHEABLE 0 /* make pages cacheable */ +#define UNCACHEABLE 1 /* make pages uncacheable */ + +#endif /* __ASM_M32R_CACHECTL */ |