diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2009-04-08 14:28:13 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-04-08 14:28:13 -0700 |
| commit | fd74ea65883c7e6903e9b652795f72b723a2be69 (patch) | |
| tree | 0792ad598080eae201d2836ac3c5a8fc46d0d03e /arch/mips/include/asm/prefetch.h | |
| parent | c8f517c444e4f9f55b5b5ca202b8404691a35805 (diff) | |
| parent | 8c6db1bbf80123839ec87bdd6cb364aea384623d (diff) | |
Merge branch 'dmaengine' into async-tx-raid6
Diffstat (limited to 'arch/mips/include/asm/prefetch.h')
| -rw-r--r-- | arch/mips/include/asm/prefetch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb0..a56594f360ee 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h @@ -26,7 +26,7 @@ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in * current versions due to erratum G105. * - * VR7701 only implements the Load prefetch. + * VR5500 (including VR5701 and VR7701) only implement load prefetch. * * Finally MIPS32 and MIPS64 implement all of the following hints. */ |