diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-04-04 10:33:41 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-04-05 09:45:08 +0200 |
| commit | aa45787c0db0a5f7b21bd16b917ff44761a2c6ac (patch) | |
| tree | 89d74fd242d65396c04eda348a7c616f8d2fb0f7 /arch/mips/kernel/smp-cps.c | |
| parent | 393a759647061bc29c1d62f83c7d36cacc912a89 (diff) | |
MIPS: smp-cps: Disable coherence setup for unsupported ISA
We don't know how to do coherence setup on ISA before MIPS
Release 1.
As CPS support only servers simulation purpose on those cores,
and simulators are always coherent, just disable initialization
code and provide user a warning in case coherence is not setup
properly.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel/smp-cps.c')
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 4fc288bb85b9..f968a319d87f 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -361,6 +361,8 @@ out: static void cps_init_secondary(void) { + int core = cpu_core(¤t_cpu_data); + /* Disable MT - we only want to run 1 TC per VPE */ if (cpu_has_mipsmt) dmt(); @@ -376,6 +378,9 @@ static void cps_init_secondary(void) BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); } + if (core > 0 && !read_gcr_cl_coherence()) + pr_warn("Core %u is not in coherent domain\n", core); + if (cpu_has_veic) clear_c0_status(ST0_IM); else |