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| author | Jani Nikula <jani.nikula@intel.com> | 2017-09-04 21:40:34 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2017-09-04 21:40:34 +0300 |
| commit | d149d6ae17197ce23e2cd6bc5fcdacf7b593e55e (patch) | |
| tree | 2fb8d66199080f6d7b41690f6e8616ccd79a1943 /arch/mips/pci/pci.c | |
| parent | afe722bee4bf8afc88c6ff7d6f781515d9428595 (diff) | |
| parent | 7846b12fe0b5feab5446d892f41b5140c1419109 (diff) | |
Merge drm-upstream/drm-next into drm-intel-next-queued
Catch up with upstream while it's easy.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'arch/mips/pci/pci.c')
| -rw-r--r-- | arch/mips/pci/pci.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index bd67ac74fe2d..9632436d74d7 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -28,16 +28,15 @@ EXPORT_SYMBOL(PCIBIOS_MIN_MEM); static int __init pcibios_set_cache_line_size(void) { - struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int lsize; /* * Set PCI cacheline size to that of the highest level in the * cache hierarchy. */ - lsize = c->dcache.linesz; - lsize = c->scache.linesz ? : lsize; - lsize = c->tcache.linesz ? : lsize; + lsize = cpu_dcache_line_size(); + lsize = cpu_scache_line_size() ? : lsize; + lsize = cpu_tcache_line_size() ? : lsize; BUG_ON(!lsize); |