Merge tag 'spi-nor/for-6.4' into mtd/next

SPI NOR core changes:
* introduce Read While Write support for flashes featuring several banks
* set the 4-Byte Address Mode method based on SFDP data
* allow post_sfdp hook to return errors
* parse SCCR MC table and introduce support for multi-chip devices

SPI NOR manufacturer drivers changes:
* macronix: add support for mx25uw51245g with RWW
* spansion:
  - determine current address mode at runtime as it can be changed in a
    non-volatile way and differ from factory defaults or from what SFDP
    advertises.
  - enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T,
    s25hx and s28hx
  - add support for s25hl02gt and s25hs02gt

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c
index f9a5a7c90ff0..64a9c093aef9 100644
--- a/arch/riscv/kernel/stacktrace.c
+++ b/arch/riscv/kernel/stacktrace.c
@@ -101,7 +101,7 @@ void notrace walk_stackframe(struct task_struct *task,
 	while (!kstack_end(ksp)) {
 		if (__kernel_text_address(pc) && unlikely(!fn(arg, pc)))
 			break;
-		pc = (*ksp++) - 0x4;
+		pc = READ_ONCE_NOCHECK(*ksp++) - 0x4;
 	}
 }