diff options
author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-06-23 09:21:15 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-06-23 09:21:15 +0200 |
commit | 58ee01007c9e00531c1280b2d99b49d29a5e9844 (patch) | |
tree | d1feb7102591a811b4458e2e209d476580ae3687 /arch/riscv/mm/fault.c | |
parent | 4850f26abfcac9ed28a4db5817b46dc0bfbbbae0 (diff) | |
parent | 4b972a01a7da614b4796475f933094751a295a2f (diff) |
Merge 5.2-rc6 into usb-next
We need the USB fixes in here too.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/riscv/mm/fault.c')
-rw-r--r-- | arch/riscv/mm/fault.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index fd7662afddea..3e2708c626a8 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -16,6 +16,7 @@ #include <asm/pgalloc.h> #include <asm/ptrace.h> +#include <asm/tlbflush.h> /* * This routine handles page faults. It determines the address and the @@ -265,6 +266,18 @@ vmalloc_fault: pte_k = pte_offset_kernel(pmd_k, addr); if (!pte_present(*pte_k)) goto no_context; + + /* + * The kernel assumes that TLBs don't cache invalid + * entries, but in RISC-V, SFENCE.VMA specifies an + * ordering constraint, not a cache flush; it is + * necessary even after writing invalid entries. + * Relying on flush_tlb_fix_spurious_fault would + * suffice, but the extra traps reduce + * performance. So, eagerly SFENCE.VMA. + */ + local_flush_tlb_page(addr); + return; } } |