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| author | Linus Walleij <linus.walleij@linaro.org> | 2014-03-14 10:26:45 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2014-03-14 10:26:45 +0100 |
| commit | 9e294427f6e427dbaf46140303acded06365f53c (patch) | |
| tree | 0669100cbd79fe8612463900171c98873d8dc454 /arch/sh/include/cpu-sh4/cpu/cache.h | |
| parent | 23600969ff137cf4c3bc9098f77e381de334e3f7 (diff) | |
| parent | fa389e220254c69ffae0d403eac4146171062d08 (diff) | |
Merge tag 'v3.14-rc6' into devel
Linux 3.14-rc6
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/cache.h')
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h index 7bfb9e8b069c..92c4cd119b66 100644 --- a/arch/sh/include/cpu-sh4/cpu/cache.h +++ b/arch/sh/include/cpu-sh4/cpu/cache.h @@ -17,7 +17,7 @@ #define SH_CACHE_COMBINED 4 #define SH_CACHE_ASSOC 8 -#define CCR 0xff00001c /* Address of Cache Control Register */ +#define SH_CCR 0xff00001c /* Address of Cache Control Register */ #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ |