diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2021-06-30 14:08:33 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-07-02 15:58:39 +0200 |
| commit | da5a9156cd2a3be2b00f8defb529ee3e35e5769b (patch) | |
| tree | bcbadc5d7dd802f839bd692f012c4b63e0a832ec /arch/x86/events/intel | |
| parent | f57191edaaeb01279a88ace1be5b7230bdd8c0ab (diff) | |
perf/x86/intel/uncore: Add Sapphire Rapids server UPI support
Sapphire Rapids uses a coherent interconnect for scaling to multiple
sockets known as Intel UPI. Intel UPI technology provides a cache
coherent socket to socket external communication interface between
processors.
The layout of the control registers for a UPI uncore unit is similar to
a M2M uncore unit.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-10-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/intel')
| -rw-r--r-- | arch/x86/events/intel/uncore_snbep.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 72ba8d44d819..20045ba723b5 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5698,6 +5698,11 @@ static struct intel_uncore_type spr_uncore_m2m = { .name = "m2m", }; +static struct intel_uncore_type spr_uncore_upi = { + SPR_UNCORE_PCI_COMMON_FORMAT(), + .name = "upi", +}; + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { @@ -5709,7 +5714,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { NULL, &spr_uncore_imc, &spr_uncore_m2m, - NULL, + &spr_uncore_upi, NULL, NULL, NULL, |