diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2021-05-26 09:40:54 -0400 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2021-05-26 09:40:54 -0400 |
| commit | abfe041de01f16d74df522d92cf5e3f6523971dd (patch) | |
| tree | 1cd997085149cf09e110baa4f98725ed18ffa05a /arch/x86/kernel/cpu/mtrr/cleanup.c | |
| parent | 7bc188cc2c8c7b21bfa0782f0d22bbf245ce1f63 (diff) | |
| parent | 9a91e5e0af5e03940d0eec72c36364a1701de240 (diff) | |
Merge drm/drm-next into drm-intel-next
Getting in sync with -rc2
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'arch/x86/kernel/cpu/mtrr/cleanup.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mtrr/cleanup.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index 0c3b372318b7..b5f43049fa5f 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -836,7 +836,7 @@ int __init amd_special_default_mtrr(void) if (boot_cpu_data.x86 < 0xf) return 0; /* In case some hypervisor doesn't pass SYSCFG through: */ - if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) + if (rdmsr_safe(MSR_AMD64_SYSCFG, &l, &h) < 0) return 0; /* * Memory between 4GB and top of mem is forced WB by this magic bit. |