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authorBorislav Petkov <bp@suse.de>2018-09-27 18:36:24 +0200
committerBorislav Petkov <bp@suse.de>2018-09-27 18:36:24 +0200
commitd913e8966a8f4b259dd6f11f0c334d865cf9d3aa (patch)
tree0b354028600f61001317426da875edc50685d36d /arch/x86/mm/tlb.c
parent6b58859419554fb824e09cfdd73151a195473cbc (diff)
parentc9661c1e80b609cd038db7c908e061f0535804ef (diff)
Merge branch 'tip-x86-hygon' into edac-for-4.20
... to pick up a dependent commit and share it with the tip tree, branch tip:x86/cpu. Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/x86/mm/tlb.c')
-rw-r--r--arch/x86/mm/tlb.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 9517d1b2a281..e96b99eb800c 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -305,6 +305,10 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
+ /* Let nmi_uaccess_okay() know that we're changing CR3. */
+ this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
+ barrier();
+
if (need_flush) {
this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
@@ -335,6 +339,9 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
if (next != &init_mm)
this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id);
+ /* Make sure we write CR3 before loaded_mm. */
+ barrier();
+
this_cpu_write(cpu_tlbstate.loaded_mm, next);
this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
}