diff options
| author | Len Brown <len.brown@intel.com> | 2016-04-06 17:15:55 -0400 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-04-07 22:18:32 +0200 |
| commit | 5a63426e2a18775ed05b20e3bc90c68bacb1f68a (patch) | |
| tree | 851ad05e09e5b5a865a6284b1d0538f17b3e1afc /crypto/hash_info.c | |
| parent | 8ae7225591fd15aac89769cbebb3b5ecc8b12fe5 (diff) | |
tools/power turbostat: print IRTL MSRs
Some processors use the Interrupt Response Time Limit (IRTL) MSR value
to describe the maximum IRQ response time latency for deep
package C-states. (Though others have the register, but do not use it)
Lets print it out to give insight into the cases where it is used.
IRTL begain in SNB, with PC3/PC6/PC7, and HSW added PC8/PC9/PC10.
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'crypto/hash_info.c')
0 files changed, 0 insertions, 0 deletions