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author | Hui Tang <tanghui20@huawei.com> | 2020-07-10 15:40:46 +0800 |
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committer | Herbert Xu <herbert@gondor.apana.org.au> | 2020-07-16 21:49:12 +1000 |
commit | 10f33d391ebd4edc861685ed0566cf807a363661 (patch) | |
tree | 6ec48e914b6d22926ed33806d05a8c7116335118 /crypto | |
parent | dadbe4c11753581d959b866198a48f5727fdc7c3 (diff) |
crypto: hisilicon/hpre - disable FLR triggered by hardware
for Hi1620 hardware, we should disable these hardware flr:
1. BME_FLR - bit 7,
2. PM_FLR - bit 11,
3. SRIOV_FLR - bit 12,
Or HPRE may goto D3 state, when we bind and unbind HPRE quickly,
as it does FLR triggered by BME/PM/SRIOV.
Fixes: c8b4b477079d("crypto: hisilicon - add HiSilicon HPRE accelerator")
Signed-off-by: Hui Tang <tanghui20@huawei.com>
Signed-off-by: Meng Yu <yumeng18@huawei.com>
Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions