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authorDan Williams <dan.j.williams@intel.com>2022-08-02 10:34:35 -0700
committerDan Williams <dan.j.williams@intel.com>2022-08-05 08:41:19 -0700
commit2901c8bdedca19e5efdab2ea55b465102231b315 (patch)
tree8362b0ecfa8f7db7278ab32f173bdee1160e25cb /drivers/cdrom/cdrom.c
parent8732947b75a826519ef33b92dbebaa3fa83e5e0b (diff)
cxl/region: Fix decoder interleave programming
Jonathan notes: "Curiously interleave ways = 1 for the EPs which is obviously wrong" ...while testing the latest CXL development branch on QEMU. It turns out the region creation process failed to program the endpoint decoders. This was missed because the default settings of x1 at 4K intereleave still results in the region appearing to function. Jonathan caught the bug by reverse mapping the translations that need to happen for the QEMU support. Link: https://lore.kernel.org/r/62e95fdf9f6e2_30440294e4@dwillia2-xfh.jf.intel.com.notmuch Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/165951146336.967013.11160153960900111443.stgit@dwillia2-xfh.jf.intel.com Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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