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authorJerome Brunet <jbrunet@baylibre.com>2024-07-19 11:42:26 +0200
committerJerome Brunet <jbrunet@baylibre.com>2024-07-29 16:47:33 +0200
commitadac147c6a32e2919cb04555387e12e738991a19 (patch)
treeeeac9cc1edb452af164b6d328a9c137e851e075f /drivers/clk/meson/vclk.c
parent4cb834703c6434c1f59156ed7b358cefaff13782 (diff)
clk: meson: introduce symbol namespace for amlogic clocks
Symbols exported by the Amlogic clock modules are only meant to be used by Amlogic clock controller drivers. Using a dedicated symbols namespace make that clear and help clean the global namespace of symbols other modules do no need. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240719094228.3985595-1-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/vclk.c')
-rw-r--r--drivers/clk/meson/vclk.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c
index e886df55d6e3..36f637d2d01b 100644
--- a/drivers/clk/meson/vclk.c
+++ b/drivers/clk/meson/vclk.c
@@ -49,7 +49,7 @@ const struct clk_ops meson_vclk_gate_ops = {
.disable = meson_vclk_gate_disable,
.is_enabled = meson_vclk_gate_is_enabled,
};
-EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
+EXPORT_SYMBOL_NS_GPL(meson_vclk_gate_ops, CLK_MESON);
/* The VCLK Divider has supplementary reset & enable bits */
@@ -134,8 +134,9 @@ const struct clk_ops meson_vclk_div_ops = {
.disable = meson_vclk_div_disable,
.is_enabled = meson_vclk_div_is_enabled,
};
-EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
+EXPORT_SYMBOL_NS_GPL(meson_vclk_div_ops, CLK_MESON);
MODULE_DESCRIPTION("Amlogic vclk clock driver");
MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(CLK_MESON);