diff options
| author | David Virag <virag.david003@gmail.com> | 2021-12-06 16:31:19 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2021-12-19 23:39:01 +0100 |
| commit | c703a2f44cce4693c8d974ed1f583143261d81c1 (patch) | |
| tree | 9dfe8a1d2927879d814308829c4b56d0f41db550 /drivers/clk/samsung/clk-pll.c | |
| parent | cfe238e4e7ff1701b010a5ff7c64ae11d53ed8cb (diff) | |
clk: samsung: clk-pll: Add support for pll1417x
pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:
PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
NULL),
Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com
Diffstat (limited to 'drivers/clk/samsung/clk-pll.c')
| -rw-r--r-- | drivers/clk/samsung/clk-pll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 83d1b03647db..70cdc87f714e 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll35xx_clk_ops; break; + case pll_1417x: case pll_0822x: pll->enable_offs = PLL0822X_ENABLE_SHIFT; pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; |