diff options
| author | Rahul Sharma <rahul.sharma@samsung.com> | 2014-03-12 20:26:46 +0530 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2014-05-14 19:16:54 +0200 |
| commit | eefe119b81eb1afb6e815818ad119cdd2d442fd3 (patch) | |
| tree | 69e37fd063f6563a4c1522797b9bd74704272ca5 /drivers/clk/samsung/clk-pll.h | |
| parent | 8432984732b59b333706fceb4cfb5123140be827 (diff) | |
clk/samsung: add support for pll2650xx
Add support for pll2650xx in samsung pll file. This PLL variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-pll.h')
| -rw-r--r-- | drivers/clk/samsung/clk-pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index ec4bc1d45e31..c0ed4d41fd90 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -32,6 +32,7 @@ enum samsung_pll_type { pll_s3c2410_upll, pll_s3c2440_mpll, pll_2550xx, + pll_2650xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ |