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authorIngo Molnar <mingo@kernel.org>2018-03-10 10:19:28 +0100
committerIngo Molnar <mingo@kernel.org>2018-03-10 10:19:28 +0100
commitd88f1f1fdb9f8f60602b406c89342e113a19df7f (patch)
tree16da02010b66f7f54fde737c5c54e43980789f79 /drivers/clocksource/arc_timer.c
parent04860d48a8aba5b21ae5ba1f86b0d4e3bc628fff (diff)
parentcdb06e9d8f520c969676e7d6778cffe5894f079f (diff)
Merge branch 'linus' into locking/core, to pick up fixes and dependencies
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/clocksource/arc_timer.c')
-rw-r--r--drivers/clocksource/arc_timer.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index 4927355f9cbe..471b428d8034 100644
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -251,9 +251,14 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
int irq_reenable = clockevent_state_periodic(evt);
/*
- * Any write to CTRL reg ACks the interrupt, we rewrite the
- * Count when [N]ot [H]alted bit.
- * And re-arm it if perioid by [I]nterrupt [E]nable bit
+ * 1. ACK the interrupt
+ * - For ARC700, any write to CTRL reg ACKs it, so just rewrite
+ * Count when [N]ot [H]alted bit.
+ * - For HS3x, it is a bit subtle. On taken count-down interrupt,
+ * IP bit [3] is set, which needs to be cleared for ACK'ing.
+ * The write below can only update the other two bits, hence
+ * explicitly clears IP bit
+ * 2. Re-arm interrupt if periodic by writing to IE bit [0]
*/
write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);