diff options
| author | Ira Weiny <ira.weiny@intel.com> | 2022-09-26 14:57:11 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-11-14 10:07:22 -0800 |
| commit | 487d828d751d90cf9ca594f45b02dd0e0d712b64 (patch) | |
| tree | fb83694896b6a27fa0fc2448a6044e041b470269 /drivers/cxl/pci.c | |
| parent | 278294798ac9118412c9624a801d3f20f2279363 (diff) | |
cxl/doe: Request exclusive DOE access
The PCIE Data Object Exchange (DOE) mailbox is a protocol run over
configuration cycles. It assumes one initiator at a time. While the
kernel has control of the mailbox user space writes could interfere with
the kernel access.
Mark DOE mailbox config space exclusive when iterated by the CXL driver.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220926215711.2893286-3-ira.weiny@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pci.c')
| -rw-r--r-- | drivers/cxl/pci.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..621a0522b554 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -418,6 +418,11 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) continue; } + if (!pci_request_config_region_exclusive(pdev, off, + PCI_DOE_CAP_SIZEOF, + dev_name(dev))) + pci_err(pdev, "Failed to exclude DOE registers\n"); + if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) { dev_err(dev, "xa_insert failed to insert MB @ %x\n", off); |