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| author | Dan Williams <dan.j.williams@intel.com> | 2023-09-14 20:29:52 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-09-15 21:45:55 -0700 |
| commit | 7914992b37d5a4b165e65a32a7723afde9356720 (patch) | |
| tree | c9036884249a9ae2e45686a7af8677109e4a3e0f /drivers/cxl/pci.c | |
| parent | 18f35dc9314db89e2d215951e5afa3e636b72baf (diff) | |
cxl/port: Quiet warning messages from the cxl_test environment
The cxl_test platform device CXL port hierarchy is useful for testing,
but throws warning messages of the form:
cxl_mem mem2: at cxl_root_port.1 no parent for dport: platform
cxl_mem mem3: at cxl_root_port.2 no parent for dport: platform
cxl_mem mem4: at cxl_root_port.3 no parent for dport: platform
cxl_mem mem5: at cxl_root_port.0 no parent for dport: platform
cxl_mem mem6: at cxl_root_port.1 no parent for dport: platform
cxl_mem mem7: at cxl_root_port.2 no parent for dport: platform
cxl_mem mem8: at cxl_root_port.3 no parent for dport: platform
cxl_mem mem9: at cxl_root_port.4 no parent for dport: platform
cxl_mem mem10: at cxl_root_port.4 no parent for dport: platform
...and this message when running testing in QEMU:
cxl_region region4: Bypassing cpu_cache_invalidate_memregion() for testing!
Noisy cxl_test warnings have caused other regressions to be missed. In
the interest of using cxl_test for early detection of dev_err() and
dev_warn() messages, silence platform device topology and
cache-invalidation messages.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pci.c')
0 files changed, 0 insertions, 0 deletions