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authorRadhey Shyam Pandey <radhey.shyam.pandey@amd.com>2023-08-07 11:21:43 +0530
committerVinod Koul <vkoul@kernel.org>2023-08-21 18:40:37 +0530
commit491e9d409629964457d094ac2b99e319d428dd1d (patch)
treee16d951095e3a8cba5ef4250180b914a3e119d9e /drivers/dma/xilinx
parentd8a3f65f6c1de1028b9af6ca31d9dd3738fda97e (diff)
dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
Increase AXI DMA transaction segments count to ensure that even in high load we always get a free segment in prepare descriptor for a DMA_SLAVE transaction. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-5-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/xilinx')
-rw-r--r--drivers/dma/xilinx/xilinx_dma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index fa31cd028df8..9bdce8fe29c8 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -178,7 +178,7 @@
#define XILINX_DMA_BD_SOP BIT(27)
#define XILINX_DMA_BD_EOP BIT(26)
#define XILINX_DMA_COALESCE_MAX 255
-#define XILINX_DMA_NUM_DESCS 255
+#define XILINX_DMA_NUM_DESCS 512
#define XILINX_DMA_NUM_APP_WORDS 5
/* AXI CDMA Specific Registers/Offsets */