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authorPing-Ke Shih <pkshih@realtek.com>2024-03-29 09:52:51 +0800
committerPing-Ke Shih <pkshih@realtek.com>2024-04-03 10:43:02 +0800
commita78d33a1286ccba088e422720e00f36b2d76dd7d (patch)
treefbfef9b22533c4d1083fd96607e086bca115d6f2 /drivers/fpga/tests
parent5b919d726b613c78d4dc463dd9f90c55843fd1b3 (diff)
wifi: rtw89: 8852c: disable PCI PHY EQ to improve compatibility
For adaption EQ circuit, this HW design and affected by EIEOS (Electrical Idle Exit Order Set) amplitude from platform and process from IC, so disable EQ to improve that. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://msgid.link/20240329015251.22762-5-pkshih@realtek.com
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