diff options
| author | Victor Lu <victorchengchi.lu@amd.com> | 2024-07-18 18:01:23 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-10-22 17:50:40 -0400 |
| commit | 8b22f048331dfd45fdfbf0efdfb1d43deff7518d (patch) | |
| tree | a3028d75468fae17f1af260e11c02f2873cfbce4 /drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | |
| parent | 0016e870542dc0a529e5ed97b628b6b727531e9b (diff) | |
drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih
Port this change to vega20_ih.c:
commit afbf7955ff01 ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts")
Original commit message:
"Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW."
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c')
0 files changed, 0 insertions, 0 deletions