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| author | Danijel Slivka <danijel.slivka@amd.com> | 2024-06-24 07:58:24 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-06-27 17:30:27 -0400 |
| commit | afbf7955ff01e952dbdd465fa25a2ba92d00291c (patch) | |
| tree | b8c0ef1bf2b1621bb292f7d8d4e2977ee85ce5f3 /drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | |
| parent | bf826ba9b4b17fb2bff507b8391a8e4babd227fa (diff) | |
drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts
Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW.
Signed-off-by: Danijel Slivka <danijel.slivka@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h')
0 files changed, 0 insertions, 0 deletions