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| author | Dmitry Osipenko <digetx@gmail.com> | 2021-06-01 07:21:07 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-08-13 12:30:33 +0200 |
| commit | 04d5d5df9df79f9045e76404775fc8a084aac23d (patch) | |
| tree | a6da54ad99589d0f23be32792103211c12a4ec20 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | |
| parent | ef531d01663a99981c4496a53f06935bead938a8 (diff) | |
drm/tegra: dc: Support memory bandwidth management
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory Controller drivers provide facility for memory bandwidth
management via interconnect API. Let's wire up the interconnect API
support to the DC driver in order to fix the distorted display output
on T30 Ouya, T124 TK1 and other Tegra devices.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: unbreak Tegra186+ display support]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h')
0 files changed, 0 insertions, 0 deletions