diff options
| author | Guchun Chen <guchun.chen@amd.com> | 2022-02-10 14:34:51 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-02-14 15:08:40 -0500 |
| commit | 22b1df28c009aaf78e77b20a9cc8d8bf98e698c8 (patch) | |
| tree | f9d1cd66699c992c0e2fb164f4f9ddc72ce57a0c /drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | |
| parent | 71579346991927687c76ff76084bcb1f9da410a2 (diff) | |
drm/amdgpu: no rlcg legacy read in SRIOV case
rlcg legacy read is not available in SRIOV configration.
Otherwise, gmc_v9_0_flush_gpu_tlb will always complain
timeout and finally breaks driver load.
v2: bypass read in amdgpu_virt_get_rlcg_reg_access_flag (from Victor)
Fixes: 97d1a3b967a3cb ("drm/amdgpu: switch to get_rlcg_reg_access_flag for gfx9")
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Victor Skvortsov <Victor.Skvortsov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index e1288901beb6..6668d7fa89e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -836,7 +836,7 @@ static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, /* only in new version, AMDGPU_REGS_NO_KIQ and * AMDGPU_REGS_RLC are enabled simultaneously */ } else if ((acc_flags & AMDGPU_REGS_RLC) && - !(acc_flags & AMDGPU_REGS_NO_KIQ)) { + !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) { *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY; ret = true; } @@ -940,7 +940,7 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev, u32 rlcg_flag; if (!amdgpu_sriov_runtime(adev) && - amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { + amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag); return; } @@ -957,7 +957,7 @@ u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, u32 rlcg_flag; if (!amdgpu_sriov_runtime(adev) && - amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) + amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag); if (acc_flags & AMDGPU_REGS_NO_KIQ) |