diff options
| author | Likun Gao <Likun.Gao@amd.com> | 2023-11-01 14:28:40 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-02 16:18:11 -0400 |
| commit | 53efeba35d71db3ef5fd4c483748945c1e765adc (patch) | |
| tree | c47452dfbde77f643eacc3278111b98e68452694 /drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | |
| parent | 1e740df77f5d4dfa75e1ca21b7ca3ebc1a907421 (diff) | |
drm/amdgpu: set different fw data addr for mec pipe
For MEC fw data, different pipe should programed into
different address.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index e8505c77e12e..68a66ccb0100 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -2432,7 +2432,9 @@ static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) return r; } - r = amdgpu_bo_create_reserved(adev, fw_data_size, + r = amdgpu_bo_create_reserved(adev, + ALIGN(fw_data_size, 64 * 1024) * + adev->gfx.mec.num_pipe_per_mec, 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, &adev->gfx.mec.mec_fw_data_obj, &adev->gfx.mec.mec_fw_data_gpu_addr, @@ -2444,7 +2446,9 @@ static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) } memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); - memcpy(fw_data_ptr, fw_data, fw_data_size); + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); + } amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); @@ -2467,9 +2471,11 @@ static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) soc24_grbm_select(adev, 1, i, 0, 0); WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, - lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); + lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + + i * ALIGN(fw_data_size, 64 * 1024))); WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, - upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); + upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + + i * ALIGN(fw_data_size, 64 * 1024))); WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); |