diff options
| author | Andrey Grodzovsky <andrey.grodzovsky@amd.com> | 2018-03-29 09:09:39 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-04-03 13:08:44 -0500 |
| commit | f7a9ee81a88b83915e7c15895c507abede44b0c5 (patch) | |
| tree | 61903e2fc7a93c70bdbd895cf12fda708cba7b31 /drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |
| parent | 073997ccd9dd8eb8015f5371ff0ea85a48814bb4 (diff) | |
drm/amdgpu: Add support for SRBM selection v3
Also remove code duplication in write and read regs functions.
This also fixes potential missing unlock in amdgpu_debugfs_regs_write
in case get_user would fail.
v2: Add SRBM mutex locking.
v3: Fix TO counter and fix comment location.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae90c95e36af..9d39fd5b1822 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -998,12 +998,19 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, start + SQIND_WAVE_VGPRS_OFFSET, size, dst); } +static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 q) +{ + soc15_grbm_select(adev, me, pipe, q, 0); +} + static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, .select_se_sh = &gfx_v9_0_select_se_sh, .read_wave_data = &gfx_v9_0_read_wave_data, .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, + .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q }; static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) @@ -2773,13 +2780,13 @@ static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) udelay(1); } - if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) { + if (j == AMDGPU_MAX_USEC_TIMEOUT) { DRM_DEBUG("KIQ dequeue request failed.\n"); + /* Manual disable if dequeue request times out */ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); } - /* Manual disable if dequeue request times out */ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0); } |